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HM514265C Series HM51S4265C Series
262,144-word x 16-bit Dynamic Random Access Memory
ADE-203-309A (Z) Rev. 1.0 Jul. 21, 1995
Description
The Hitachi HM51(S)4265C is a CMOS dynamic RAM organized 262,144-word x 16-bit. HM51(S)4265C has realized higher density, higher performance and various functions by employing 0.8 m CMOS process technology and some new CMOS circuit design technologies. The HM51(S)4265C offers Extended Data Out (EDO) Page Mode as a high speed access mode. Multiplexed address input permits the HM51(S)4265C to be packaged in standard 400-mil 40-pin plastic SOJ and standard 400-mil 44-pin plastic TSOPII. Internal refresh timer enables HM51S4265C self reflesh operation.
Features
* * * Single 5 V (10%) (HM51(S)4265C-6/7/8) (5%) (HM51(S)4265C-6R) High speed -- Access time: 60 ns/70 ns/80 ns (max) Low power dissipation -- Active mode: 825 mW/788 mW/770 mW/688 mW (max) -- Standby mode: 11 mW (max) (HM51(S)4265C-6/7/8) 10.5 mW (max) (HM51(S)4265C-6R) 1.1 mW (max) (L-version) (HM51(S)4265CL-6/7/8) 1.05 mW (max) (L-version) (HM51(S)4265CL-6R) EDO page mode capability 512 refresh cycles : 8 ms 128 ms (L-version) 2 variations of refresh -- RAS-only refresh -- CAS-before-RAS refresh 2CAS-byte control Battery backup operation (L-version) Self refresh operation (HM51S4265C)
* * *
* * *
HM514265C, HM51S4265C Series
Ordering Information
Type No. HM514265CJ-6 HM514265CJ-6R HM514265CJ-7 HM514265CJ-8 HM514265CLJ-6 HM514265CLJ-6R HM514265CLJ-7 HM514265CLJ-8 HM51S4265CJ-6 HM51S4265CJ-6R HM51S4265CJ-7 HM51S4265CJ-8 HM51S4265CLJ-6 HM51S4265CLJ-6R HM51S4265CLJ-7 HM51S4265CLJ-8 HM514265CTT-6 HM514265CTT-6R HM514265CTT-7 HM514265CTT-8 HM514265CLTT-6 HM514265CLTT-6R HM514265CLTT-7 HM514265CLTT-8 HM51S4265CTT-6 HM51S4265CTT-6R HM51S4265CTT-7 HM51S4265CTT-8 HM51S4265CLTT-6 HM51S4265CLTT-6R HM51S4265CLTT-7 HM51S4265CLTT-8 Access time 60 ns 60 ns 70 ns 80 ns 60 ns 60 ns 70 ns 80 ns 60 ns 60 ns 70 ns 80 ns 60 ns 60 ns 70 ns 80 ns 60 ns 60 ns 70 ns 80 ns 60 ns 60 ns 70 ns 80 ns 60 ns 60 ns 70 ns 80 ns 60 ns 60 ns 70 ns 80 ns 400-mil 44-pin plastic TSOPII (TTP-44/40DB) Package 400-mil 40-pin plastic SOJ (CP-40DA)
2
HM514265C, HM51S4265C Series
Pin Arrangement
HM514265CJ/CLJ Series HM51S4265CJ/CLJ Series VCC I/O0 I/O1 I/O2 I/O3 VCC I/O4 I/O5 I/O6 I/O7 NC NC WE RAS NC A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VSS I/O15 I/O14 I/O13 I/O12 VSS I/O11 I/O10 I/O9 I/O8 NC LCAS UCAS OE A8 A7 A6 A5 A4 VSS HM514265CTT/CLTTSeries HM51S4265CTT/CLTTSeries VCC I/O0 I/O1 I/O2 I/O3 VCC I/O4 I/O5 I/O6 I/O7 1 2 3 4 5 6 7 8 9 10 44 43 42 41 40 39 38 37 36 35 VSS I/O15 I/O14 I/O13 I/O12 VSS I/O11 I/O10 I/O9 I/O8
(Top view)
NC NC WE RAS NC A0 A1 A2 A3 VCC
13 14 15 16 17 18 19 20 21 22
32 31 30 29 28 27 26 25 24 23
NC LCAS UCAS OE A8 A7 A6 A5 A4 VSS
(Top view)
Pin Description
Pin name A0 -A8 Function Address input -- Row address -- Column address -- Refresh address Data-in/data-out Row address strobe Column address strobe Read/write enable Output enable Power (+5 V) Ground No connection A0 - A8 A0 - A8 A0 - A8
I/O0 - I/O15 RAS UCAS, LCAS WE OE VCC VSS NC
3
HM514265C, HM51S4265C Series
Block Diagram
I/O Bus & Column Decoder
I/O Bus & Column Decoder
I/O Bus & Column Decoder
I/O Bus & Column Decoder
256 k Memory Array Mat
256 k Memory Array Mat
256 k Memory Array Mat
256 k Memory Array Mat
256 k Memory Array Mat
256 k Memory Array Mat
256 k Memory Array Mat
Row Decoder
Row Row Decoder Decoder
Row Decoder
Row Decoder
Row Row Decoder Decoder
Row Decoder
Selector
Selector
Selector
Selector
I/O4
I/O4 Buffer I/O5 Buffer I/O6 Buffer I/O7 Buffer
256 k Memory Array Mat
I/O11 Buffer
Peripheral Circuit
I/O3 I/O3 Buffer
I/O2 I/O2 Buffer
I/O1 I/O1 Buffer
I/O0 I/O0 Buffer
I/O15 I/O15 Buffer
I/O14 I/O14 Buffer
I/O13 I/O13 Buffer
I/O12 I/O12 Buffer
I/O11
I/O5
I/O10 I/O10 Buffer I/O9 Buffer I/O8 Buffer I/O9
I/O6
I/O7
I/O8
Peripheral Circuit WE RAS Address A0,A1,A2,A3 Address A4,A5 A6,A7,A8
LCAS UCAS OE
Selector
Row Decoder
Selector
Row Decoder
Selector
Row Decoder
Selector
Row Decoder
Row Row Decoder Decoder
Row Row Decoder Decoder
I/O Bus & Column Decoder
I/O Bus & Column Decoder
I/O Bus & Column Decoder
I/O Bus & Column Decoder
256 k Memory Array Mat
256 k Memory Array Mat
256 k Memory Array Mat
256 k Memory Array Mat
256 k Memory Array Mat
256 k Memory Array Mat
256 k Memory Array Mat
Operation Mode
The HM51(S)4265C series has the following 11 operation modes.
4
256 k Memory Array Mat
Peripheral Circuit
HM514265C, HM51S4265C Series
1. Read cycle 2. Early write cycle 3. Delayed write cycle 4. Read-modify-write cycle 5. RAS-only refresh cycle 6. CAS-before-RAS refresh cycle 7. Self refresh cycle (HM51S4265C) 8. EDO page mode read cycle 9. EDO page mode early write cycle 10. EDO page mode delayed write cycle 11. EDO page mode read- modify-write cycle
Inputs RAS H H L L L L L H to L LCAS H L L L L L H H L L L L L L L H to L H to L H to L H to L L UCAS H L L L L L H L H L H to L H to L H to L H to L L H L L
*2 *2
WE D H H L L
*2 *2
OE D L L D H L to H D D
Output Open Valid Valid Open Undefined Valid Open Open
Operation Standby Standby Read cycle Early write cycle Delayed write cycle Read-modify-write cycle RAS-only refresh cycle CAS-before-RAS refresh cycle Self refresh cycle (HM51S4265C)
H to L D D
L D H L to H H
Valid Open Undefined Valid Open
EDO page mode read cycle EDO page mode early write cycle EDO page mode delayed write cycle EDO page mode read-modify-write cycle Read cycle (Output disabled)
H to L H
Notes: 1. H: High(inactive) L: Low(active) D: H or L 2. t WCS 0 ns Early write cycle t WCS < 0 ns Delayed write cycle 3. Mode is determined by the OR function of the UCAS and LCAS. (Mode is set by the earliest of UCAS and LCAS active edge and reset by the latest of UCAS and LCAS inactive edge.) However write OPERATION and output HIZ control are done independently by each UCAS, LCAS. ex. if RAS = H to L, LCAS = L, UCAS = H, then CAS-before-RAS refresh cycle is selected.
5
HM514265C, HM51S4265C Series
Absolute Maximum Ratings
Parameter Voltage on any pin relative to V SS Supply voltage relative to VSS Short circuit output current Power dissipation Operating temperature Storage temperature Symbol VT VCC Iout PT Topr Tstg Value -1.0 to +7.0 -1.0 to +7.0 50 1.0 0 to +70 -55 to +125 Unit V V mA W C C
Recommended DC Operating Conditions (Ta = 0 to +70C)
Parameter Supply voltage Symbol VSS VCC (HM51(S)4265C-6/7/8) VCC (HM51(S)4265C-6R) Input high voltage Input low voltage VIH VIL Min 0 4.5 4.75 2.4 -1.0 Typ 0 5.0 5.0 -- -- Max 0 5.5 5.25 6.5 0.8 Unit V V V V V 1, 2 1, 2 1 1 Notes
Notes: 1. All voltage referred to VSS . 2. The supply voltage with all VCC pins must be on the same level. The supply voltage with all VSS pins must be on the same level.
6
HM514265C, HM51S4265C Series
DC Characteristics (Ta = 0 to 70C, VCC = 5 V 5%, VSS = 0 V) (HM51(S)4265C6R) (Ta = 0 to +70C, VCC = 5 V 10%, VSS = 0 V) (HM51(S)4265C-6/7/8)
HM514265C, HM51S4265C -6/6R Parameter Operating current
*1, *2
-7 Max Min 150 --
-8 Max Min 140 -- Max Unit Test conditions 125 mA RAS cycling UCAS or LCAS cycling t RC = min TTL interface RAS, UCAS, LCAS = VIH Dout = High-Z CMOS interface RAS, UCAS, LCAS, WE, OE V CC - 0.2 V Dout = High-Z CMOS interface RAS, UCAS, LCAS, WE, OE VCC - 0.2 V Dout = High-Z t RC = min RAS = VIH, UCAS or LCAS = VIL Dout = enable t RC = min t HPC = min Standby: CMOS interface Dout = High-Z CBR refresh: tRC = 250 s t RAS 1 s, UCAS, LCAS = VIL WE, OE = VIH CMOS interface RAS, UCAS, LCAS 0.2 V, Dout = High-Z CMOS interface RAS, UCAS, LCAS 0.2 V, Dout = High-Z 0 V Vin 7 V 0 V Vout 7 V Dout = disable High Iout = -2 mA Low Iout = 2 mA
Symbol Min I CC1 --
Standby current
I CC2
--
2
--
2
--
2
mA
--
1
--
1
--
1
mA
Standby current (Lversion)
I CC2
--
200
--
200
--
200
A
RAS-only refresh current*2 I CC3 Standby current
*1
-- --
140 5
-- --
130 5
-- --
110 5
mA mA
I CC5
CAS-before-RAS refresh current*2
*3
I CC6
-- -- --
140 180 300
-- -- --
130 150 300
-- -- --
110 130 300
mA mA A
EDO page mode current *1, I CC4 Battery backup current *4 (Standby with CBR refresh) (L-version) I CC10
Self-refresh mode current (HM51S4265C) Self-refresh mode current (HM51S4265CL) Input leakage current Output leakage current Output high voltage Output low voltage
I CC11
--
1
--
1
--
1
mA
I CC11
--
200
--
200
--
200
A
I LI I LO VOH VOL
-10 -10 2.4 0
10 10 VCC 0.4
-10 -10 2.4 0
10 10 VCC 0.4
-10 -10 2.4 0
10 10 VCC 0.4
A A V V
Notes: 1. I CC depends on output load condition when the device is selected. ICC max is specified at the output open condition.
7
HM514265C, HM51S4265C Series
2. 3. 4. 5. Address can be changed twice or less while RAS = VIL. Address can be changed once or less within one EDO page cycle. VIH VCC - 0.2 V, 0 VIL 0.2 V, Address can be changed once or less while RAS = VIL. All the V CC pins should be supplied with the same voltage. And all the VSS pins should be supplied with the same voltage.
Capacitance (Ta = +25C, VCC = 5 V 5%) (HM51(S)4265C-6R) (Ta = +25C, VCC = 5 V 10%) (HM51(S)4265C-6/7/8)
Parameter Input capacitance (Address) Input capacitance (Clocks) Output capacitance (Data-in, Data-out) Symbol CI1 CI2 CI/O Typ -- -- -- Max 5 7 10 Unit pF pF pF Notes 1 1 1, 2
Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. RAS, UCAS and LCAS = VIH to disable Dout.
AC Characteristics (Ta = 0 to +70C, VCC = 5 V 5%, VSS = 0 V) (HM51(S)4265C-6R)*1, *14, *15, *17, *18 (Ta = 0 to +70C, VCC = 5 V 10%, VSS = 0 V) (HM51(S)4265C-6/7/8)*1, *14, *15, *17, *18
Test Conditions * * * * * Input rise and fall time : 2 ns Input level : V IL = 0 V, V IH = 3.0 V Input timing reference levels : 0.8 V, 2.4 V Output timing reference levels : 0.8 V, 2.0 V Output load : 1 TTL gate + CL (50 pF) (Including scope and jig)
8
HM514265C, HM51S4265C Series
Read, Write, Read-Modify-Write and Refresh Cycles (Common parameters)
HM514265C, HM51S4265C -6/-6R Parameter Random read or write cycle time RAS precharge time RAS pulse width CAS pulse width Row address setup time Row address hold time Column address setup time Column address hold time RAS to CAS delay time RAS to column address delay time RAS hold time CAS hold time CAS to RAS precharge time OE to Din delay time OE delay time from Din CAS setup time from Din Transition time (rise and fall) Refresh period Refresh period (L-version) Symbol Min Max t RC t RP t RAS t CAS t ASR t RAH t ASC t CAH t RCD t RAD t RSH t CSH t CRP t ODD t DZO t DZC tT t REF t REF 104 -- 40 60 10 0 10 0 10 20 15 15 48 10 15 0 0 2 -- -- -- 10000 10000 -- -- -- -- 45 30 -- -- -- -- -- -- 50 8 128 -7 Min Max 124 -- 50 70 13 0 10 0 13 20 15 18 58 10 18 0 0 2 -- -- -- 10000 10000 -- -- -- -- 50 35 -- -- -- -- -- -- 50 8 128 -8 Min Max 144 -- 60 80 15 0 10 0 15 20 15 20 68 10 20 0 0 2 -- -- -- 10000 10000 -- -- -- -- 60 40 -- -- -- -- -- -- 50 8 128 Unit Notes ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ms 7 29 20 19 19 8 9 27 28
9
HM514265C, HM51S4265C Series
Read Cycle
HM514265C, HM51S4265C -6/-6R Parameter Access time from RAS Access time from CAS Access time from address Access time from OE Read command setup time Read command hold time to CAS Read command hold time to RAS Column address to RAS lead time Column address to CAS lead time Output buffer turn-off time Output buffer turn-off time to OE CAS to Din delay time RAS to Din delay time WE to Din delay time OE pulse width Turn-off to RAS Turn-off to WE Output data hold time Output data hold time from RAS Symbol Min Max t RAC t CAC t AA t OAC t RCS t RCH t RRH t RAL t CAL t OFF1 t OFF2 t CDD t RDD t WDD t OEP t OFR t WEZ t OH t OHR -- -- -- -- 0 0 0 30 18 -- -- 15 15 15 15 -- -- 5 5 60 15 30 60 15 30 15 -- -- -- -- -- 15 15 -- -- -- -- 15 15 -- -- -- -- -- -7 Min Max -- -- -- -- 0 0 0 35 23 -- -- 18 18 18 20 -- -- 5 5 70 18 35 70 20 35 20 -- -- -- -- -- 15 15 -- -- -- -- 15 15 -- -- -- -- -- -8 Min Max -- -- -- -- 0 0 0 40 28 -- -- 20 20 20 20 -- -- 5 5 80 20 40 80 20 40 20 -- -- -- -- -- 15 15 -- -- -- -- 15 15 -- -- -- -- -- Unit Notes ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 23 6, 25 6 6, 25 6 2, 3 3, 4, 13 3, 5, 13 23 19 16, 19 16
Read command hold time from RAS t RCHR Read command hold time from CAS t RCHC Read command hold time from column address t RCHA
10
HM514265C, HM51S4265C Series
Write Cycle
HM514265C, HM51S4265C -6/-6R Parameter Write command setup time Write command hold time Write command pulse width Write command to RAS lead time Write command to CAS lead time Data-in setup time Data-in hold time Symbol Min Max t WCS t WCH t WP t RWL t CWL t DS t DH 0 10 10 10 10 0 10 -- -- -- -- -- -- -- -7 Min Max 0 13 10 13 13 0 13 -- -- -- -- -- -- -- -8 Min Max 0 15 10 15 15 0 15 -- -- -- -- -- -- -- Unit Notes ns ns ns ns ns ns ns 21 11 11 10, 19 19
Read-Modify-Write Cycle
HM514265C, HM51S4265C -6/-6R Parameter Read-modify-write cycle time RAS to WE delay time CAS to WE delay time Column address to WE delay time OE hold time from WE Symbol Min Max t RWC t RWD t CWD t AWD t OEH 133 -- 77 32 47 15 -- -- -- -- -7 Min Max 159 -- 90 38 55 18 -- -- -- -- -8 Min Max 183 -- 102 -- 42 62 20 -- -- -- Unit Notes ns ns ns ns ns 10 10 10
Refresh Cycle
HM514265C, HM51S4265C -6/-6R Parameter CAS hold time (CBR refresh cycle) RAS precharge to CAS hold time Symbol Min Max 10 10 10 10 -- -- -- -- CAS setup time (CBR refresh cycle) t CSR t CHR t RPC -7 Min Max 10 10 10 13 -- -- -- -- -8 Min Max 10 10 10 15 -- -- -- -- Unit Notes ns ns ns ns 19 20 19 22
CAS precharge time in normal mode t CPN
11
HM514265C, HM51S4265C Series
EDO Page Mode Cycle
HM514265C, HM51S4265C -6/-6R Parameter EDO page mode cycle time EDO page mode CAS precharge time EDO page mode RAS pulse width Access time from CAS precharge RAS hold time from CAS precharge Output data hold time from CAS low CAS hold time referred OE CAS to OE setup time Read command hold time from CAS precharge Symbol Min Max t HPC t CP t RASC t ACP t RHCP t DOH t COL t COP t RCHP 25 10 -- -- 35 3 10 5 35 -- -- -7 Min Max 30 13 -- -- -8 Min Max 35 15 -- -- Unit Notes ns ns 12 3, 13, 17 24
100000 -- 35 -- -- -- -- -- -- 40 3 13 5 40
100000 -- 40 -- -- -- -- -- -- 45 3 20 5 45
100000 ns 45 -- -- -- -- -- ns ns ns ns ns ns
26
EDO Page Mode Read-Modify-Write Cycle
HM514265C, HM51S4265C -6/-6R Parameter EDO page mode read-modify-write cycle time EDO page mode read-modify-write cycle CAS precharge to WE delay time Symbol Min Max t HPCM t CPW 66 52 -- -- -7 Min Max 77 60 -- -- -8 Min Max 86 67 -- -- Unit Notes ns ns 10
Self Refresh Mode
HM51S4265C -6/-6R Parameter RAS pulse width (self refresh) RAS precharge time (self refresh) CAS hold time (self refresh) Symbol Min Max t RASS t RPS t CHS 100 -- 110 -- -50 -- -7 Min Max 100 -- 130 -- -50 -- -8 Min Max 100 -- 150 -- -50 -- Unit Notes ns ns ns 21 30, 31, 32
12
HM514265C, HM51S4265C Series
Notes: 1. AC measurements assume t T = 2 ns. 2. Assumes that t RCD tRCD (max) and tRAD tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, t RAC exceeds the value shown. 3. Measured with a load circuit equivalent to 1 TTL loads and 50 pF. 4. Assumes that t RCD tRCD (max) and tRAD tRAD (max). 5. Assumes that t RCD tRCD (max) and tRAD tRAD (max). 6. t OFF1 (max), tOFF2 (max), tOFR (max) and tWEZ (max) define the time at which the output achieves the open circuit condition and is not referred to output voltage levels. 7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between V IH and VIL. 8. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a reference point only, if tRCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC . 9. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a reference point only, if tRAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA . 10. t WCS , t RWD, t CWD and t AWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only: if t WCS tWCS (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if t RWD t RWD (min), tCWD tCWD (min), tAWD tAWD (min) and tCPW tCPW (min), the cycle is a read-modifywrite and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 11. These parameters are referred to CAS leading edge in an early write cycle and to WE leading edge in a delayed write or a read-modify-write cycle. 12. t RASC defines RAS pulse width in EDO page mode cycles. 13. Access time is determined by the longest among t AA , t CAC and t ACP. 14. An initial pause of 100 s is required after power up followed by a minimum of eight initialization cycles (RAS-only refresh cycle or CAS-before-RAS refresh cycle). If the internal refresh counter is used, a minimum of eight CAS-before-RAS refresh cycles is required. 15. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to the device. 16. Either t RCH or tRRH must be satisfied for a read cycle. 17. When both UCAS and LCAS go low at the same time, all 16-bit data are written into the device. UCAS and LCAS cannot be staggered within the same write/read cycles. 18. All the V CC and VSS pins shall be supplied with the same voltages. 19. t ASC, tCAH , t RCS , t RCH, t WCS , t WCH, t CSR and t RPC are determined by the earlier falling edge of UCAS or LCAS. 20. t CRP , t CHR, t ACP, tRCH and t CPW are determined by the later rising edge of UCAS or LCAS. 21. t CWL, t DH, t DS and t CHS should be satisfied by both UCAS and LCAS. 22. t CPN and t CP are determined by the time that both UCAS and LCAS are high. 23. When output buffers are enabled once, sustain the low impedance state until valid data is obtained. When output buffer is turned on and off within a very short time, generally it causes large V CC/V SS line noise, which causes to degrade V IH min/VIL max level. 24. t HPC (min) can be achieved during a series of EDO page mode early write cycles or EDO page mode read cycles. If both write and read operation are mixed in a EDO page mode RAS cycle (EDO page mode mix cycle (1), (2)), minimum value of CAS cycle tHPC (tCAS + tCP + 2tT) becomes greater than the specified t HPC (min) value. 25. t OFF1 and t OFR are determined by the later rising edge of RAS or CAS. 26. t DOH defines the time at which the output level satisfies the output timing reference levels. Measured with the test conditions. 27. t RAS (min) = tRWD (min) + tRWL (min) + tT in read-modify-write cycle. 28. t CAS (min) = tCWD (min) + tCWL (min) + tT in read-modify-write cycle. 29. t CSH (min) can be achieved when tRCD tCSH (min) - tCAS (min).
13
HM514265C, HM51S4265C Series
30. If you use distributed CBR refresh mode with 15.6 s interval in normal read/write cycle, CBR refresh should be executed within 15.6 s immediately after exiting from and before entering into self refresh mode. 31. If you use RAS only refresh or CBR burst refresh mode in normal read/write cycle, 512 cycles of distributed CBR refresh with 15.6 s interval should be executed within 8 ms immediately after exiting from and before entering into the self refresh mode. 32. Repetitive self refresh mode without refreshing all memory is not allowed. Once you exit from self refresh mode, all memory cells need to be refreshed before re-entering the self refresh mode again. 33. H or L (H: VIH (min) V IN V IH (max), L: VIL (min) V IN V IL (max)) Invalid Dout
A @ A @
14
HM514265C, HM51S4265C Series
Notes concerning 2CAS control
1. Each of the UCAS/LCAS should satisfy the timing specifications individually. 2. Different operation mode for upper/lower byte is not allowed; such as following.
RAS Delayed write UCAS Early write LCAS
WE
3. Closely separated upper/lower byte control is not allowed. However when the condition (t CP tUL) is satisfied, fast page mode can be performed.
RAS
UCAS
LCAS t UL
15
HM514265C, HM51S4265C Series
Timing Waveforms*33
Read Cycle
t RC t RAS
RAS tT t RCD t RSH t CAS t CSH t RP t CRP
UCAS LCAS t RAD t ASR t RAH t ASC t RAL t CAH
Address
Row
Column t CAL t RCHR t RCHC t RCHA t OHR t RCH t RRH t CAC t AA t OFR t OFF1 Dout t RAC t DZC t OAC High-Z t WDD t DZO t OEP t ODD t OFF2 t CDD t WEZ t OH t RDD
t RCS
WE
Dout
Din
OE
16
HM514265C, HM51S4265C Series
Early Write Cycle
t RC t RAS
RAS tT t RCD t CSH UCAS LCAS t RSH t CAS
t RP t CRP
t ASR
t RAH
tASC
t CAH
Address
Row
Column
t WCS
t WCH
WE
t DS
t DH
Din
Din
Dout
High-Z*
* t WCS
t WCS (min)
** OE : H or L
17
HM514265C, HM51S4265C Series
Delayed Write Cycle
t RC t RAS
t RP
RAS t CSH t RCD tT UCAS LCAS t ASR t RAH t ASC t CAH Column t CWL t RWL t RSH t CAS t CRP
Address
Row
t RCS
t WP
WE t DS
t DH
t DZC t DZO t ODD t OEH Dout
Invalid Dout*
Din
High-Z
Din
t OFF2
OE
*
* Invalid Dout comes out, when OE is low level.
Read-Modify-Write Cycle
18
HM514265C, HM51S4265C Series
t RWC t RAS t RP
RAS tT t RCD t CAS t CRP
UCAS LCAS t ASR
t RAD t RAH t ASC tCAH
Address
Row t RCS
Column t CWD t AWD t CWL t RWL t WP
WE t RWD t RAC t DZC Din
High-Z
t AA t CAC t DS t DH
Din
Dout t OAC
Dout
t OFF2 t DZO OE t OEP t ODD
t OEH
19
HM514265C, HM51S4265C Series
EDO Page Mode Read Cycle (tHPC minimum cycle operation)
t RASC t RHCP t RP
RAS tT t CSH t RCD UCAS LCAS t ASR t RAD t RAH Address Row tASC t CAL t CAH Column 1 t CAL t ASC t CAH Column 2 t ASC t CAL t RAL t CAH Column 3 t RCHA t RCS WE t DZC t WEZ t CDD Din t CAC t RAC t AA High-Z t CAC t AA t ACP t DOH Dout t OAC t DZO t OFF2 Dout 1 t CAC t AA t ACP t DOH Dout 2 t OFR t RCHP t RCHC t RRH t RCH t CAS t CP t HPC t CAS t CP t RSH t CAS t CRP
t OH t ODD t OHR
t OFF1 Dout 3
OE
20
HM514265C, HM51S4265C Series
EDO Page Mode Read Cycle (High-Z control by WE and OE)
t RP
RAS
t RASC tT t CSH t CAS t RCS t RCHR t RCHC t RCHA tASR tRAH t ASC tCAH Row tDZC Column 1 tCAL High-Z t ASC t CAH
Column 2
t HPC t HPC tCAS t RCHP t RHCP t CP tCAS t RRH t RCH t t RAL RCHC t ASC t CAH
Column 3
t CP
t HPC t CAS
t CRP
t CP
UCAS LCAS
t RCH t RCS
WE
tASC
t CAH
Column 4
t WDD
Address
t CAL
t CAL
t CAL
tRDD tCDD
Din
tDZO
tCOL
tCOP tODD
OE
tOAC tCAC tAA tRAC
Dout
tACP tAA tCAC tWEZ tOFF2 tOAC Dout 2
tACP tACP tAA tCAC tDOH Dout 2
Dout 3
tAA tOFF2 tCAC tOAC Dout 4
tOFR tOHR tOFF2 tOFF1 tOH
Dout 1
21
HM514265C, HM51S4265C Series
EDO Page Mode Early Write Cycle (tHPC minimum cycle operation)
t RASC t RP
RAS tT t CSH t RCD UCAS LCAS t CAS t CP t HPC t CAS t CP t RSH t CAS t CRP
t ASR
t RAH
t ASC
t CAH
t ASC
t CAH
t ASC
t CAH
Address
Row
Column
Column
Column
t WCS
t WCH
t WCS
t WCH t WCS
t WCH
WE
t DS
t DH
t DS
t DH
t DS
t DH
Din
Din
Din
Din
Dout
High-Z
* OE : H or L
22
HM514265C, HM51S4265C Series
EDO Page Mode Delayed Write Cycle
t RASC
t RP
RAS tT tRCD t CSH t CAS t HPC t CP t CAS t CP t RSH t CAS t CRP
UCAS LCAS t ASR t RAH t ASC t CAH Column t CWL t RCS t WP WE t DH t DS t RCS t DS t DH t RCS t DS Din t DH t ASC t CAH t ASC t CAH
Address
Row
Column t CWL t WP
Column t CWL t WP t RWL
Din
Din
Din t OEH
Dout t ODD
High-Z
OE
23
HM514265C, HM51S4265C Series
EDO Page Mode Read-Modify-Write Cycle
t RP
t RASC RAS t RCD tT t CAS t RAD t RAH t ASR t CAH t ASC t ACP t ASC t CAH t CAH t ASC t CP t CAS t HPCM t CP t CAS
t CRP
UCAS LCAS
Address
Row
Column t AWD t CWD t RWD t CWL t WP t RCS
Column t AWD t CWD t CPW t CWL t WP
Column t CPW t AWD t RCS t CWD t CWL t RWL t WP
t RCS
WE t CAC t DS t DH High-Z tAA t RAC tOAC Dout t DZO Dout t OFF2 t DZO t OEH t OAC Dout t OFF2 t OEH t DZC t CAC High-Z t AA t DS t DH t ACP t DZC High-Z t CAC t AA t OAC Dout t OFF2 t OEH t DS t DH
t DZC
Din
Din
Din
Din
t DZO
OE t ODD t OEP t OEP t ODD tOEP t ODD
24
HM514265C, HM51S4265C Series
EDO Page Mode Mix Cycle (1)*24
t RP
RAS
t RASC tT t CSH t CAS t WCS t WCH tCPW tAWD tASR t ASC tRAH Row tCAH t ASC t CAH Column 2 t CAL High-Z tODD tASC t CAH Column 3 t CAL t DS t DH tWP tASC t CP t CAS t CP tCAS t CP tCAS t RCHP t RCHC t RCHA t RAL t CAH Column 4 t CAL tRDD tCDD t RRH t RCH t CRP
UCAS LCAS
WE
Address
Column 1 tCAL t DH Din 1
t DS
Din
Din 3 tWDD
OE
t ACP tAA tOAC tCAC
tDZO t ACP tAA tCAC t DOH tOFF2
tACP tAA tCAC tOAC
tOFR tWEZ tOFF2 tOFF1 tOH Dout 4
Dout
Dout 2
Dout 3
25
HM514265C, HM51S4265C Series
EDO Page Mode Mix Cycle (2)*24
t RP
RAS
t RASC tT t CSH t CAS t RCS t RCHR t RCH t WCS t WCH tCPW tASR t ASC tRAH Row tCAH t ASC t CAH Column 2 t DS t CAL t DH Din 2 tODD tDZO tODD t ASC t CAH Column 3 t CAL t DS t DH t CP t CAS t CP tCAS tCWL tWP tASC t CP tCAS t RCHP t RCHC t RCHA t RAL t CAH Column 4 t CAL tRDD tCDD t RRH t RCH t CRP
UCAS LCAS
WE
Address
Column 1 tCAL High-Z
Din
Din 3 tDZO tWDD
OE
tAA tOAC tCAC tRAC
tOFF2
t OAC tACP tAA tCAC
tACP tOFF2 tAA tCAC tOAC
tOFR tWEZ tOFF2 tOFF1 tOH Dout 4
Dout
Dout 1
Dout 3
26
HM514265C, HM51S4265C Series
CAS-Before-RAS Refresh Cycle
t RC t RP t RAS ** t RP t RC t RAS ** t RP
RAS tT t RPC t CPN LCAS t RPC t CSR t CHR t CPN t CSR t CHR t CRP
UCAS Address t OFF1 Dout High-Z * WE : H or L 27
> ** Do not extend tRAS _ tRAS (max). Untested self refresh mode may be activated and loss of data may be resulted (HM514265C).
HM514265C, HM51S4265C Series
RAS-Only Refresh Cycle
t RC t RAS t RP
RAS tT t CRP tRPC tCRP
UCAS LCAS t ASR t RAH
Address
Row
Dout
High-Z
* Refresh address : A0 - A8 (AX0 - AX8) ** WE : H or L
28
HM514265C, HM51S4265C Series
Self Refresh Cycle
t RP
t RASS
t RPS
RAS tT t RPC t CPN UCAS LCAS t CRP t CSR t CHS
Address t OFF1 Dout High-Z 29
* WE, OE : H or L
The low self refresh current is achieved by introducing extremely long internal refresh cycle. Therefore some care needs to be taken on the refresh. 1.Please do not use tRASS timing, 10 s tRASS 100 s. During this period, the device is in transition state from normal operation mode to self refresh mode. If tRASS 100 s, then RAS precharge time should use tRPS instead of tRP. 2.If you use RAS only refresh or CBR burst refresh mode in normal read/write cycle, 512 cycles of distributed CBR refresh with 15.6 s interval should be executed within 8 ms immediately after exiting from and before entering into the self refresh mode. 3. If you use distributed CBR refresh mode with 15.6 s interval in normal read/write cycle, CBR refresh should be executed within 15.6 s immediately after exiting from and before entering into self refresh mode. 4.Repetitive self refresh mode without refreshing all memory is not allowed. Once you exit from self refresh mode, all memory cells need to be refreshed before re-entering the self refresh mode again.
HM514265C, HM51S4265C Series
Package Dimension
HM514265CJ/CLJ Series (CP-40DA)
Unit: mm
25.80 26.16 Max 40 21 10.16 0.13 0.74
1.30 Max 3.50 0.26
1
20
11.18 0.13
0.43 0.10
1.27 0.10
0.80
9.40 0.25
HM514265CTT/CLTT Series (TTP-44/40DB)
2.85 0.12
+0.25 -0.17
Unit: mm
44
18.41 18.81 Max 35 32
23
1
10 13 0.80 0.13 M 1.005 Max
22
0.27 0.07
10.16
11.76 0.20 0 - 5 0.13 0.05
+0.075 -0.025
1.20 Max
0.10
0.145
0.50 0.10
30
0.68
0.80

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